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? semiconductor components industries, llc, 2002 february, 2002 rev. 5 1 publication order number: mc14511b/d mc14511b bcd-to-seven segment latch/decoder/driver the mc14511b bcdtoseven segment latch/decoder/driver is constructed with complementary mos (cmos) enhancement mode devices and npn bipolar output drivers in a single monolithic structure. the circuit provides the functions of a 4bit storage latch, an 8421 bcdtoseven segment decoder, and an output drive capability. lamp test (lt ), blanking (bi ), and latch enable (le) inputs are used to test the display, to turnoff or pulse modulate the brightness of the display, and to store a bcd code, respectively. it can be used with sevensegment lightemitting diodes (led), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly. applications include instrument (e.g., counter, dvm, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. ? low logic circuit power dissipation ? highcurrent sourcing outputs (up to 25 ma) ? latch storage of code ? blanking input ? lamp test provision ? readout blanking on all illegal input combinations ? lamp intensity modulation capability ? time share (multiplexing) facility ? supply voltage range = 3.0 v to 18 v ? capable of driving two lowpower ttl loads, one lowpower schottky ttl load or two htl loads over the rated temperature range ? chip complexity: 216 fets or 54 equivalent gates ? triple diode protection on all inputs maximum ratings (voltages referenced to v ss ) (note 2) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in input voltage range, all inputs 0.5 to v dd + 0.5 v i dc current drain per input pin 10 ma p d power dissipation, per package (note 3) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c i ohmax maximum output drive current (source) per output 25 ma p ohmax maximum continuous output power (source) per output (note 4) 50 ma 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c 4. p ohmax = i oh (v dd v oh ) http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14511bcp pdip16 2000/box mc14511bd soic16 48/rail mc14511bdw soic16 47/rail 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14511bcp awlyyww mc14511bdwr2 soic16 1000/tape & reel soic16 dw suffix case 751g 1 16 14511b awlyyww soeiaj16 f suffix case 966 1 16 mc14511b alyw soic16 d suffix case 751b 1 16 14511b awlyww mc14511bf soeiaj16 see note 1 mc14511bfel soeiaj16 see note 1
mc14511b http://onsemi.com 2 this device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit. a destructive high current mode may occur if v in and v out are not constrained to the range v ss (v in or v out ) v dd . due to the sourcing capability of this circuit, damage can occur to the device if v dd is applied, and the outputs are shorted to v ss and are at a logical 1 (see maximum ratings). unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 b a g f v dd e d c bi lt c b v ss a d le 0123456789 display a b c d e fg inputs outputs le bi lt d c b a a b c d e f g display xx0xxxx1111111 8 x 0 1 x x x x 0 0 0 0 0 0 0 blank 01100001111110 0 01100010110000 1 01100101111001 2 01100111111001 3 01101000110011 4 01101011011011 5 01101100011111 6 01101111110000 7 01110001111111 8 01110011110011 9 0 1 1 1 0 1 0 0 0 0 0 0 0 0 blank 0 1 1 1 0 1 1 0 0 0 0 0 0 0 blank 0 1 1 1 1 0 0 0 0 0 0 0 0 0 blank 0 1 1 1 1 0 1 0 0 0 0 0 0 0 blank 0 1 1 1 1 1 0 0 0 0 0 0 0 0 blank 0 1 1 1 1 1 1 0 0 0 0 0 0 0 blank 111xxxx * * x = don't care * depends upon the bcd code previously applied when le = 0 truth table
mc14511b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (note 5) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.1 9.1 14.1 e e e 4.1 9.1 14.1 4.57 9.58 14.59 e e e 4.1 9.1 14.1 e e e vdc input voltage # a0o level (v o = 3.8 or 0.5 vdc) (v o = 8.8 or 1.0 vdc) (v o = 13.8 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 3.8 vdc) (v o = 1.0 or 8.8 vdc) (v o = 1.5 or 13.8 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive voltage (i oh = 0 ma) source (i oh = 5.0 ma) (i oh = 10 ma) (i oh = 15 ma) (i oh = 20 ma) (i oh = 25 ma) v oh 5.0 4.1 e 3.9 e 3.4 e e e e e e e 4.1 e 3.9 e 3.4 e 4.57 4.24 4.12 3.94 3.70 3.54 e e e e e e 4.1 e 3.5 e 3.0 e e e e e e e vdc (i oh = 0 ma) (i oh = 5.0 ma) (i oh = 10 ma) (i oh = 15 ma) (i oh = 20 ma) (i oh = 25 ma) 10 9.1 e 9.0 e 8.6 e e e e e e e 9.1 e 9.0 e 8.6 e 9.58 9.26 9.17 9.04 8.90 8.70 e e e e e e 9.1 e 8.6 e 8.2 e e e e e e e vdc (i oh = 0 ma) (i oh = 5.0 ma) (i oh = 10 ma) (i oh = 15 ma) (i oh = 20 ma) (i oh = 25 ma) 15 14.1 e 14 e 13.6 e e e e e e e 14.1 e 14 e 13.6 e 14.59 14.27 14.18 14.07 13.95 13.70 e e e e e e 14.1 e 13.6 e 13.2 e e e e e e e vdc output drive current (v ol = 0.4 v) sink (v ol = 0.5 v) (v ol = 1.5 v) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance c in e e e e 5.0 7.5 e e pf quiescent current (per package) v in = 0 or v dd , i out = 0 m a i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (notes 6 & 7) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.9 m a/khz) f + i dd i t = (3.8 m a/khz) f + i dd i t = (5.7 m a/khz) f + i dd m adc 5. noise immunity specified for worstcase input combination. noise margin for both a1o and a0o level = 1.0 vdc min @ v dd = 5.0 vdc 2.0 vdc min @ v dd = 10 vdc 2.5 vdc min @ v dd = 15 vdc 6. the formulas given are for the typical characteristics only at 25 c. 7. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + 3.5 x 10 3 (c l 50) v dd f where: i t is in m a (per package), c l in pf, v dd in vdc, and f in khz is input frequency.
mc14511b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (note 8) (c l = 50 pf, t a = 25 c) characteristic symbol v dd vdc min typ max unit output rise time t tlh = (0.40 ns/pf) c l + 20 ns t tlh = (0.25 ns/pf) c l + 17.5 ns t tlh = (0.20 ns/pf) c l + 15 ns t tlh 5.0 10 15 e e e 40 30 25 80 60 50 ns output fall time t thl = (1.5 ns/pf) c l + 50 ns t thl = (0.75 ns/pf) c l + 37.5 ns t thl = (0.55 ns/pf) c l + 37.5 ns t thl 5.0 10 15 e e e 125 75 65 250 150 130 ns data propagation delay time t plh = (0.40 ns/pf) c l + 620 ns t plh = (0.25 ns/pf) c l + 237.5 ns t plh = (0.20 ns/pf) c l + 165 ns t plh 5.0 10 15 e e e 640 250 175 1280 500 350 ns t phl = (1.3 ns/pf) c l + 655 ns t phl = (0.60 ns/pf) c l + 260 ns t phl = (0.35 ns/pf) c l + 182.5 ns t phl 5.0 10 15 e e e 720 290 200 1440 580 400 blank propagation delay time t plh = (0.30 ns/pf) c l + 585 ns t plh = (0.25 ns/pf) c l + 187.5 ns t plh = (0.15 ns/pf) c l + 142.5 ns t plh 5.0 i0 15 e e e 600 200 150 750 300 220 ns t phl = (0.85 ns/pf) c l + 442.5 ns t phl = (0.45 ns/pf) c l + 177.5 ns t phl = (0.35 ns/pf) c l + 142.5 ns t phl 5.0 10 15 e e e 485 200 160 970 400 320 lamp test propagation delay time t plh = (0.45 ns/pf) c l + 290.5 ns t plh = (0.25 ns/pf) c l + 112.5 ns t plh = (0.20 ns/pf) c l + 80 ns t plh 5.0 10 15 e e e 313 125 90 625 250 180 ns t phl = (1.3 ns/pf) c l + 248 ns t phl = (0.45 ns/pf) c l + 102.5 ns t phl = (0.35 ns/pf) c l + 72.5 ns t phl 5.0 10 15 e e e 313 125 90 625 250 180 setup time t su 5.0 10 15 100 40 30 e e e e e e ns hold time t h 5.0 10 15 60 40 30 e e e e e e ns latch enable pulse width t wl 5.0 10 15 520 220 130 260 110 65 e e e ns 8. the formulas given are for the typical characteristics only.
mc14511b http://onsemi.com 5 figure 1. dynamic power dissipation signal waveforms input le low, and inputs d, bi and lt high. f in respect to a system clock. all outputs connected to respective c l loads. 20 ns 20 ns v dd v ss v oh v ol 90% 50% 10% 50% a, b, and c any output 50% duty cycle 1 2f figure 2. dynamic signal waveforms 20 ns 20 ns v dd 90% input c (a) inputs d and le low, and inputs a, b, bi and lt high. v ss v oh v ol 50% 10% output g t plh t phl 90% 10% 50% t tlh t thl (b) input d low, inputs a, b, bi and lt high. 20 ns 10% 90% 50% v dd v ss v dd v ss v oh v ol t h t su 50% input c output g le (c) data dcba strobed into latches. 20 ns 20 ns v dd v ss le 90% 50% 10% t wl
mc14511b http://onsemi.com 6 connections to various display readouts common cathode led 1.7 v v dd v ss v dd common anode led v ss 1.7 v light emitting diode (led) readout incandescent readout fluorescent readout gas discharge readout liquid crystal (lcd) readout v dd v dd ** v ss v dd v ss filament supply direct (low brightness) v ss or appropriate voltage below v ss . (caution: maximum working voltage = 18.0 v) v dd appropriate voltage v ss v ss v dd excitation (square wave, v ss to v dd ) 1/4 of mc14070b ** a filament prewarm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. direct dc drive of lcd's not recommended for life of lcd readouts.
mc14511b http://onsemi.com 7 figure 3. logic diagram le5 d6 c2 b1 a7 v dd = pin 16 v ss = pin 8 bi 4 lt3 14g 15f 9e 10d 11c 12b 13a
mc14511b http://onsemi.com 8 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14511b http://onsemi.com 9 package dimensions soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14511b http://onsemi.com 10 package dimensions soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14511b http://onsemi.com 11 package dimensions soeiaj16 f suffix plastic eiaj soic package case 96601 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc14511b http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14511b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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